1. Field of the Invention
The present invention relates to a tuner device including a plurality of tuner circuits.
2. Description of the Related Art
A tuner device included in a television receiver selects the signal of a desired channel from among high frequency signals of television broadcasting, the high frequency signals including a very high frequency (VHF) signal, an ultra high frequency (UHF) signal, and so forth that are received through an antenna, performs frequency conversion for the selected signal so that the selected signal is converted into an intermediate frequency signal, and externally transmits the intermediate frequency signal.
FIG. 5 shows an exemplary internal configuration of a tuner device 2 according to a related art. The tuner device 2 includes an antenna 21, an input end T11, a tuner circuit 22, a demodulator 23, an output end T12, and receives a terrestrial television broadcast wave.
In the tuner device 2, a radio frequency (RF) signal SRF transmitted from the antenna 21 is transmitted to the tuner circuit 22 via the input end T11 and subjected to band limitation through a band-pass filter (BPF) 301. The band-limited RF signal is subjected to signal amplification through an RF amplifier 302, and subjected to frequency conversion through a mixer (frequency mixing circuit) 303 so that an intermediate frequency (IF) signal is obtained. The IF signal is band-limited through an IF filter 304, amplified through an IF amplifier 305, demodulated to a baseband signal SB through the demodulator 23, and externally transmitted from the output end T12.
The tuner device 2 includes a phase locked loop (PLL) 306 functioning as a local oscillation circuit, and transmits a local oscillation signal fOSC to the mixer 303. In the PLL 306, a reference signal transmitted from a reference signal source 306A via a 1/M (where the sign M indicates an arbitrary integer greater than or equal to two) frequency divider 306B and a signal transmitted from a voltage controlled oscillator (VCO) 306E via a 1/N (where the sign N indicates an arbitrary integer greater than or equal to two) frequency divider 306F functioning as a comparison signal source are transmitted to a phase frequency detector 306C. The phase frequency detector 306C compares the phase of the reference signal transmitted from the reference signal source 306A via the 1/M frequency divider 306B to that of the signal transmitted from the VCO 306E via the 1/N frequency divider 306F. Then, the phase frequency detector 306C externally transmits the phase difference as a pulse signal. The pulse signal is smoothed through a low pass filter (LPF) 306D, and the smoothed current and voltage of the signal is transmitted to the VCO 306E. Thus, a local oscillation frequency fOSC of the local oscillation signal SOSC oscillated by the PLL 306 is controlled.
Here, in the PLL 306, assuming that the reference frequency of the reference signal source 306A is determined to be fREF, and a frequency obtained by dividing the reference frequency fREF at a ratio of 1/M is compared to a frequency obtained by dividing a frequency fOSC transmitted from the VCO 306E at a ratio of 1/N. In that case, the integer M of the 1/M frequency divider 306B and the integer N of the 1/N frequency divider 306F are made variable so that a local oscillation frequency having an arbitrary value obtained through the calculation fREF×N/M is obtained, as disclosed in Japanese Unexamined Patent Application Publication No. 2004-214715.